Dag - a cell capture board for ATM measurement systems.

Ian D Graham, Murray Pearson, Jed Martens and Stephen Donnelly
The University of Waikato
Hamilton
New Zealand

April, 1997

Abstract

This paper describes in outline the design of an ATM cell capture card designed for measurement applications. The present version of the card is hosted by an ATML PCI-bus NIC, and consists of a Xilinx FPGA and physical layer devices for OC3 and DS3/E3 rate ATM. A stand-alone PCI bus measurement card is being developed.

Introduction

For some time staff in the Department of Computer Science at the University of Waikato have been working on the problems of the efficient simulation of ATM networks. Most of our work has been done through the Canadian Telesim project [1], however we have also been supported by New Zealand Telecom and its OPERA ATM trial network project[2].

About two years ago it became clear that we needed measurements of actual ATM traffic to verify the traffic models used in the simulation, and to investigate claims of self-similarity. Unfortunately, the cost of conventional ATM test and measurement equipment is very high, and was beyond our budget. However, we were able to obtain detailed information on the hardware of the Advanced Telecommunications Ltd (ATML) [3] range of Network Interface Cards (NICs), and to program these cards to measure accurately the arrival times of ATM cells. Initially we worked only at 25 Mbps, but were later able to extend our work by obtaining two experimental 155 Mbps NICs from ATML.

As well as measuring cell arrivals at a single point we are able to use synchronised measurement points to measure time delay through a network. The measurement cards are synchronised using a 1 Hz clock. For local measurements this clock is derived from a simple oscillator, for measurements between remote sites the clock is provided by a Global Position System (GPS) time receiver. We use a pair of Trimble Navigation Palisade systems [4], for which an accuracy of ±100 nS and resolution of 40 nS is claimed by the manufacturer. This fits well within our measurement resolution of 250 nS.

To recognise individual cells we compute a CRC over the cell payload, under error-free conditions this will not change as the cell traverses the network. This means that we can use existing traffic on the network to measure cell delay and delay variation, and detect lost or added cells. Cell arrival events captured by the NIC cards are transferred to a PC, and then to a UNIX system for further analysis. We also program NICs to act as traffic generators, for situations where existing traffic is insufficient, or unsuitable, for timing measurements.

Much of this work is described in [5] and on our Web site [6].

The Dag board

The Dag board is part of our progression to the production of an independent ATM measurement card. The present version relies on the use of an ATML PCI-bus NIC to provided the processor and PCI interface; the next version may be built around the ATMLŐs Hydrogen ATM-on-a-chip device [3].

The Dag consists of physical layer devices for DS3/E3 and OC3 ATM, a large Xilinx FPGA, and a 32-bit wide interface to the ATML NIC. The internal logic of the Xilinx is still under development, but a sketch of it is shown in figure 1

Each cell received by one of the physical layer interfaces is read by the cell multiplexer and filter. If the cell passes the filter parameters it is stored in the next free block of the cell buffer. As each cell arrives a time stamp is generated, and a cell payload CRC is computed as the payload bytes of the cell are read. These values are stored in the buffer along with the cell header and payload. Time signals are received from the GPS receiver at a 1 Hz rate. These also generate time stamps, which can be post-processed to correct the internal clock time stamps to UTC.

The ARM 610 processor [7] on the NIC has direct access to the cell buffers in the Xilinx. The processor can read any word of the cell, the header, CRC or time stamp, and can also read the whole cell at a higher speed by DMA. With the 32 MHz ARM processor the complete contents of a cell buffer can be read into its memory in less than 1.25 mS

Data may be transferred from the ARM memory into the host PCŐs memory by DMA over the PCI bus, or by PCI Direct Master operation. DMA transfers are more efficient for large transfers, but require more setup time than direct master operation.

Programming the system

With a fully loaded ATM link at 155 Mbps a cell will arrive in the device roughly every 2.8 mS. This places very strict requirements on the software and firmware. The requirements of a measurement card are rather different from those of a normal NIC, which is mostly concerned with the assembly of AAL5 SDUs, and passing on these large data structures to the host processor.

The system may be programmed at four levels:

Each of these levels of programming must be optimised for the particular operation. The Xilinx is used to off-load from the ARM processor as much as possible the task of processing cells, and to provide the fastest possible interface from the ARM to the cell payload. The ARM processor can execute perhaps 40 instructions per cell time, the exact number depending on how many of these instructions are loads or stores. If the entire cell has to be read there is time to execute only about 20 ARM instructions. Very little processing can usually be done in the PC; its job is to act as a large data buffer, in memory and on disk. However, simple procedures such as a traffic meter can be run on the PC concurrently with cell capture.

Acknowledgements

This work has been supported by the University of Waikato, New Zealand Telecom, the Foundation for Research, Science and Technology, and the New Zealand Lotteries Board. Thanks are also due to ATM Ltd, for access to detailed information on their network interface cards.

References and Web sites

[1] Telesim project: http://www.wnet.ca/telesim/
[2] OPERA ATM trial: http://www.opera.net.nz/
[3] ATML Ltd: http://www.atml.co.uk/
[4] Trimble Navigation: http://www.trimble.com/
[5] Waikato ATM project: http://phoenix.cs.waikato.ac.nz/atm/
[6] Ian D Graham and John G Cleary, 1996. Cell level measurements of ATM traffic in Proceedings of the Australian Telecommunications Networks and Applications Conference, 1996, pp 495-500. Monash University, Melbourne
[7] The ARM processor: http://www.arm.com/

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