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Mark Will's blog

09

Dec

2012

This week I've managed to implement the NTP protocol in hardware since the version of the ntp code we got only sent arp responses. So it sends valid ntp packets now, checksums and all. I also discovered it was replying to any IP address so this has been fixed as well. Towards the end of the week I've started looking at getting the code running on a Spartan 6 board to test the server while we wait for the Ethernet cards for the Zedboards.

01

Dec

2012

We have decided to order some GigE daughter boards for the Zedboard since the on board one can't be wired to the FPGA. We have figured out how to make the NTP hardware configurable via the Linux OS running on the arm system. I've tested the hardware and Jack's being working on the driver so hopefully we can test that fully soon. I have also figured out the version of the NTP code we have currently only sends arp responses so I have started modifying that and testing via simulation.

27

Nov

2012

This weeks been a big week for me, not to do with the project though. I turned 21 and got my first hole in one out at Ngahinapouri Golf Course. But back to the project, its been another slow week however the tools seem to be working now. I've managed to figure out how the clock management (MMCM) works on the boards. The real setback at the moment is we're not sure how to use the on board NIC within the programmable logic. I have posted on a forum and hopefully get a reply soon.

17

Nov

2012

It's my first week working on the NTP FPGA project. I've written a few test Verilog modules to get familiar with programming the board and have done a lot of reading about how to configure it to work with Anthony's VHDL code. Sadly the Xilinx tools aren't working probably at the moment so getting anything meaningful on the board hasn't happen yet.